FEDL7074-003FULL-01
OKI Semiconductor
ML7074-003 GA
PCM I/F Mode
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta = −20 to +60°C)
Parameter
Bit clock frequency
Bit clock duty ratio
Symbol
fBCLK
dBCLK
fSYNC
Conditions
CDL = 20pF(at output)
CDL = 20pF(at output)
CDL = 20pF(at output)
CDL = 20pF(at output)
At 64 kHz output
CDL = 20pF(at output)
At 128 kHz output
BCLK to SYNC
(at output)
Min.
−0.1%
45
Typ.
64
50
8
Max.
+0.1%
55
Unit
kHz
%
+0.1%
kHz
Sync signal frequency
−0.1%
dSYNC1
dSYNC2
tBS
12.4
6.24
100
100
12.5
6.25
12.6
6.26
%
%
Sync signal duty ratio
ns
ns
Transmit/receive signal sync
timing
SYNC to BCLK
(at output)
tSB
Input setup time
Input hold time
tDS
tDH
tSDX
tXD1
tXD2
tXD3
100
100
—
—
100
100
100
100
ns
ns
ns
ns
ns
ns
Digital output delay time
Digital output hold time
PCMO pin
Pull-up, pull-down resistors
RDL = 1 kΩ, CDL = 50 pF
BCLK
0
1
2
3
4
5
6
7
8
-
16
tBS tSB
tWS
SYNC
PCMI
tDS tDH
MSB
LSB
G.726
LSB
G.711
LSB
16-bit
linear
Fig. 2 PCM I/F mode input timing (long frame)
BCLK
0
1
2
3
4
5
6
7
8
9
-
17
tBS tSB
tWS
SYNC
PCMI
tDS tDH
MSB
LSB
G.726
LSB
G.711
LSB
16-bit
linear
Fig. 3 PCM I/F mode input timing (short frame)
13/31
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