FEDL70512-04
OKI Semiconductor
ML70512
CLK and Configuration
Pin Name
RESET
DETACH
SCLKO
Direc-
tion
I
I
O
Internal
Pull Up/
Down,
Schmitt
Schmitt
Schmitt
—
Initial
Value
—
—
—
Pin Placement
Description
ML70512HB
K8
J8
B10
ML70512LA
G10
G8
H3
Hardware reset pin (Reset = L)
Sleep pin (Sleep = L)
System clock (12/13/16 MHz) output
pins
[*1]
[*2]
[*3]
[*4]
SFRQSEL0: G2; SFRQSEL1: A6
SFRQSEL0: C7; SFRQSEL1: F2
RFSEL0: J9; RFSEL1: H8; RFSEL2: K10
RFSEL0: H10; RFSEL1: H8; RFSEL2: K10
PCM I/F
Pin Name
PCMOUT
PCMIN
PCMSYNC
Direc-
tion
O
I
I/O
Internal
Pull Up/
Down,
Schmitt
—
Pull up
Pull
down
Pull
down
Initial
Value
L
—
—
Pin Placement
Description
ML70512HB
C9
E8
D10
ML70512LA
J4
H5
K4
PCM data output
PCM data input
PCM sync signal (8 kHz),
Initial setting: input
(can be switched by an internal register)
PCM clock (64 kHz/128 kHz)
Initial setting: input
(can be switched by an internal register)
PCMCLK
I/O
—
D9
H4
Note: The PCM sync signal (8 kHz) must be guaranteed at the accuracy of
±50
ppm if the PCMSYNC pin is
configured as an input.
UART I/F
Pin Name
SOUT
SIN
RTS
CTS
Direc-
tion
O
I
O
I
Internal
Pull Up/
Down,
Schmitt
—
Schmitt
—
—
Initial
Value
H
—
—
H
Pin Placement
Description
ML70512HB
B5
B7
J10
H6
ML70512LA
E1
F1
K9
J9
ACE transmit serial data
ACE receive serial data
ACE transmit data ready
ACE transmit ready
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