FEDL70512-04
OKI Semiconductor
ML70512
CLK and Configuration
Internal
Pull Up/
Down,
Schmitt
Schmitt
Schmitt
Pin Placement
Direc-
tion
Initial
Value
Pin Name
Description
ML70512HB ML70512LA
RESET
I
I
—
—
K8
J8
G10
G8
Hardware reset pin (Reset = L)
Sleep pin (Sleep = L)
DETACH
System clock (12/13/16 MHz) output
pins
SCLKO
O
—
—
B10
H3
[*1] SFRQSEL0: G2; SFRQSEL1: A6
[*2] SFRQSEL0: C7; SFRQSEL1: F2
[*3] RFSEL0: J9; RFSEL1: H8; RFSEL2: K10
[*4] RFSEL0: H10; RFSEL1: H8; RFSEL2: K10
PCM I/F
Internal
Pin Placement
ML70512HB ML70512LA
Direc-
tion
Initial
Value
Pull Up/
Down,
Schmitt
—
Pin Name
Description
PCMOUT
PCMIN
O
I
L
C9
E8
J4
PCM data output
Pull up
—
H5
PCM data input
PCM sync signal (8 kHz),
Initial setting: input
(can be switched by an internal register)
PCM clock (64 kHz/128 kHz)
Initial setting: input
Pull
down
PCMSYNC
PCMCLK
I/O
I/O
—
—
D10
D9
K4
H4
Pull
down
(can be switched by an internal register)
Note: The PCM sync signal (8 kHz) must be guaranteed at the accuracy of ±50 ppm if the PCMSYNC pin is
configured as an input.
UART I/F
Internal
Pin Placement
Direc-
tion
Initial
Value
Pull Up/
Down,
Schmitt
—
Pin Name
Description
ML70512HB ML70512LA
SOUT
SIN
O
I
H
—
—
H
B5
B7
E1
F1
K9
J9
ACE transmit serial data
ACE receive serial data
ACE transmit data ready
ACE transmit ready
Schmitt
—
RTS
CTS
O
I
J10
H6
—
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