FEDL7022-01-06
1
Semiconductor
ML7022-01
PIN DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
V
DD
TEST1
TEST2
AIN1
GSX1
AOUT1
TEST3
AG
SGC
AOUT2
GSX2
AIN2
TEST4
TEST5
V
DD
TEST6
C1B
C2B
C3B
MCK
BCLK
DIN
DOUT
DG
XSYNC
RSYNC
C3A
C2A
C1A
PDN
Type
—
I
I
I
O
O
I
—
O
O
O
I
I
I
—
I
O
O
O
I
I
I
O
—
I
I
O
O
O
I
Power Supply *
Device Test Pin 1
Device Test Pin 2
Channel-1 Transmit Op-amp Input
Channel-1 Transmit Op-amp Output
Channel-1 Receive Output
Device Test Pin 3
Analog Ground
Signal Ground
Channel-2 Receive Output
Channel-2 Transmit Op-amp Output
Channel-2 Transmit Op-amp Input
Device Test Pin 4
Device Test Pin 5
Power Supply *
Device Test Pin 6
C1B Bit Latched Output
C2B Bit Latched Output
C3B Bit Latched Output
Master Clock (4.096 MHz)
Shift Clock for the DIN and DOUT
Data Input
Data Output
Digital Ground
Transmit Synchronizing Signal
Receive Synchronizing Signal
C3A Bit Latched Output
C2A Bit Latched Output
C1A Bit Latched Output
Power Down Control
Description
* V
DD
of pin 1 and V
DD
of pin 15 are connected internally, but these pins must be connected on the printed
circuit board.
4/20
OKI [ OKI ELECTRONIC COMPONETS ]
