FEDL7029-03
OKI Semiconductor
ML7029
MCK
Master clock input.
The frequency is 1296 times the SYNC signal. For example, it is 10.368 MHz when the SYNC signal is 8 kHz.
The master clock signal may be asynchronous with BCLK and SYNC.
PCMSO
Transmit PCM data output.
PCM is output from MSB in synchronization with the rising edge of BCLK and XSYNC.
Refer to Figure 1. During power-down, the PCMSO output is at “L” level.
PCMSI
Transmit PCM data input.
This signal is converted to the transmit ADPCM data, PCM is shifted in synchronization with the falling edge of
BCLK. Normally, this pin is connected to PCMSO. Refer to Figure 1.
PCMRO
Receive PCM data output.
PCM is the output signal after ADPCM decoder processing. This signal is output serially from MSB in
synchronization with the rising edge of BCLK and RSYNC. Refer to Figure 1.
During power-down, the PCMRO output is at “L” level.
PCMRI
Receive PCM data input.
PCM is shifted on the rising edge of the BCLK and input from MSB. Normally, this pin is connected to PCMRO.
Refer to Figure 1.
IS
Transmit ADPCM signal output.
After having encoded PCM with ADPCM, the signal is output from MSB in synchronization with the rising edge
of BCLK and XSYNC. Refer to Figure 1. This pin is at “H” level during power-down.
IR
Receive ADPCM signal input.
This input signal is shifted serially on the falling edge of BCLK and SYNC and input from MSB. Refer to Figure
1.
BCLK
Shift clock input for the PCM and ADPCM data.
The frequency is set in the range of 8 to 256 times the SYNC frequency. Refer to Figure 1.
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