¡ Semiconductor
ML7021
Serial Output Timing
fSCK, tSCK
tDSC
SCK
tSX
tXS
tCYC
SYNC
tWSY
tXD
tSD
tXD
tXD
SOUT
ROUT
High-Z
High-Z
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
Operation Timing After Reset
tWR
*Reset timing can be asynchronous
tDIT
RST
tDRS
Internal operaion
tDRE
Reset
Initialization
Processing Start
Note: INT is invalid in the diagonally shaded interval.
Power Down Timing
PWDWN
tDPS
tDPE
Internal Operation
Power Down
Processing Start
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