FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
Primary /
Secondary
Pin Name
I/O
Description
Logic
DMA control signals
DREQ[0]
I
Ch 0 DMA request signal, used when DMA controller configured for
DREQ type
Secondary
Secondary
Positive
Positive
DREQCLR[0]
O
Ch 0 DREQ signal clear request. The DMA device responds to this
output by negating DREQ.
TCOUT[0]
DREQ[1]
O
I
Indicates to Ch 0 DMA device that last transfer has started.
Secondary
Secondary
Positive
Positive
Ch 1 DMA request signal, used when DMA controller configured for
DREQ type
DREQCLR[1]
O
O
Ch 1 DREQ signal clear request. The DMA device responds to this
output by negating DREQ.
Secondary
Secondary
Positive
Positive
TCOUT[1]
UART
SIN
Indicates to Ch 1 DMA device that last transfer has started
I
O
I
SIO receive signal
SIO transmit signal
Clear To Send.
Secondary
Secondary
Secondary
Positive
Positive
Negative
SOUT
CTS
Indicates that modem or data set is ready to transfer data.
modem status register reflects this input.
Bit 4 in
DSR
DCD
DTR
I
I
Data Set Ready.
Secondary
Secondary
Secondary
Negative
Negative
Negative
Indicates that modem or data set is ready to establish a
communications link with UART.
Bit 5 in modem status register reflects this input.
Data Carrier Detect.
Indicates that modem or data set has detected data carrier signal. Bit
7 in modem status register reflects this input.
Data Carrier Detect
O
Data Terminal Ready.
Indicates that UART is ready to establish a communications link with
modem or data set. Bit 0 in modem control register controls this
output.
RTS
RI
O
I
Request To Send.
Secondary
Secondary
Negative
Negative
Indicates that UART is ready to transfer data to modem or data set. Bit
1 in modem control register controls this output.
Ring Indicator. Indicates that modem or data set has received
telephone ring indicator. Bit 6 in modem status register reflects this
input.
SIO
STXD
O
I
SIO transmit signal
SIO receive signal
Secondary
Secondary
Positive
Positive
SRXD
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