Oki Semiconductor
ML674000
SPECIFICATION OVERVIEW
CPU
32-bit RISC (ARM7TDMI)
32-bit mode (ARM instructions) and/or 16-bit mode (Thumb instructions)
General purpose registers : 31 x 32 bits
Barrel shifter and multiplier (32 bit x 8 bit)
Little endian
On-chip debug and in-circuit-emulation (ICE)
8 KB of SRAM; 32-bit single clock access
Glueless connectivity to the following:
ROM (Flash): up to 16 MBytes
SRAM: up to 16 MBytes
DRAM: up to 64 MBytes (SDRAM and EDO DRAM support)
External IO devices: up to 16 MBytes x 2 banks (with wait control by external
signal). Programmable wait setting by each bank.
24 sources: 19 internal and 5 external (IRQ: 4, FIQ: 1)
8 level priority, inidividually maskable
2 channels; Supports dual address mode transfers, burst mode and cycle steel
7 channels: 16-bit auto reload for application
1 channel: 16 bit watchdog timer
1 channel UART with Tx and Rx signals only
1 channel: asynchronous with 16-Byte FIFO
2 channels x 16 bits
2 channels x 16 bits
8 channels x 10 bits
Standby and Halt (halting of clock to each block is configurable independently)
Clock ratio (selectable 1/1, 1/2, 1/4, 1/8, 1/16 input clock frequency)
Porivdes access to the on-chip ICE (In Circuit Emulation)
Core: 2.25 V to 2.75 V, I/O section: 3.0 V to 3.6 V
33 MHz (Maximum)
–40°C to +85°C
128-pin plastic TQFP (TQFP128-P-1414-0.40-K)
144-pin plastic LFBGA (P-LFBGA144-1111-0.80)
Internal memory
External memory controller
Interrupt controller
DMA controller
Timers
Serial I/O interface
UART
GPIO
PWM
A to D converter
Power down mechanism
JTAG interface
Power supply voltage
Operating frequency
Operating temp (ambient)
Package
2/22
OKI [ OKI ELECTRONIC COMPONETS ]
