8. Sep, 1998
ML63326
PRELIMINARY
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied to the
circuits corresponding to the signal names inside
from V
DDI
( power supply for interface ) .
nX-4/250
TIMING
CONTROL
SP
RSP
STACK
CAL.S:16-level
REG.S:16-level
RESET
TST1
TST2
XT0
XT1
OSC0
OSC1
V
DDH
V
DD
CB1
CB2
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
C1
C2
V
DDL
AOUT
AOUTB
MD
MDB
VREF
Multiplexer
12bit DAC
REGU-
LATOR
DATA BUS
BLD
INT
1
INT
1
BIAS
INT
1
MELODY
LCD
&
DSPR
VOICE
INTERFACE
WDT
100Hz TC
OUTPUT
PORT
INT
2
I/O PORT
ALU
MIE
INSTRUCTION
DECODER
IR
INT
4
RESET
TEST
OSCL
INT
OSCH
4
TBC
RAM
1536×4bits
INT326
INT
1
SFT
INT
1
CBR
EBR
H
X
L
Y
C
RA
A
G
Z
BUS
CON-
TROL
PC
ROM
24K×16bits
EXTMEM
D0 to D7*
A0 to A15*
RD*
WR*
TIMER
8bit×4
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
SIN*
SOUT*
SCLK*
INPUT
PORT
P0.0 to P0.3
P4.0 to P4.3
P5.0 to P5.3
P6.0 to P6.3
P7.0 to P7.3
P8.0,P8.1
P9.0 to P9.3
PA.0 to PA.3
PB.0 to PB.3
PE.0 to PE.3
PF.0 to PF.3
COM1 to 16
SEG0 to 63
V
DDI
V
SS
BUSY
LPF
Phrase
Address
Latch
Multiplexer
PCM
Synthesizer
Address
Controller
MELODY
ADPCM
Synthesizer
17bit
Multiplexer
1Mbit ROM
The voice synthesis portion
17bit
Address
Counter
4 of 4
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