Semiconductor
ML63293 Preliminary Ver.1.1 Feb.10,1999
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function.
nX-4/250
TIMING
CON-
TROL
CBR
EBR
H
X
L
RA
A
PC
ROM
64KW
Y
SP
C
G
Z
BUS
CON-
TROL
ALU
D0 - D7*
EXTMEM
RSP
MIE
64KB
A0 - A15*
INSTRUCTION
DECODER
STACK
CAL.S:16-level
REG.S:16-level
RD*
WR*
IR
INT
4
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
TIMER
8bit (4ch)
RAM
3KN
T13CK*
INT
2
RXC*
TXC*
RXD*
TXD*
SIO
INT
1
INT293
SCLK*
SIN*
SFT
RESET
RST
SOUT*
MULDIV
TBC
INT
1
INT
4
MD
MDB
TST1
TST2
MELODY
TST
INPUT
PORT
INT
1
P0.0
- P0.3
BLD
XT0
XT1
INT
1
P4.0 - P4.3
P5.0 - P5.3
P6.0 - P6.3
P7.0 - P7.3
OSC
OSC0
100HzTC
WDT
OUTPUT
PORT
OSC1
INT
1
VDDH
VDD
CB1
P8.0 - P8.3
P9.0 - P9.3
PA.0 - PA.3
PB.0 - PB.3
PC.0 - PC.3
PE.0 - PE.3
BACK
UP
I/O
PORT
CB2
INT
4
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
LCD
&
DSPR
COM1 - 32
SEG0 - 67
BIAS
C1
C2
VDDI
VSS
VDDL
5 of 5
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