FEDL63193-04
Semiconductor
1
ML63193
• I/O Ports
Input ports:
Selectable as input pull-up resistor/input pull-down resistor/high impedance input.
I/O ports:
Selectable as input pull-up resistor/input pull-down resistor/high impedance input.
Selectable as P-channel open drain output/N-channel open drain output/high-impedance output/
CMOS output.
Can be interfaced with external peripherals that use a different power supply than this device uses.V
DDI
is the
power supply pin for ports.
Number of ports:
Input port
: 1 port × 4 bits
Input-output port
: 5 ports × 4 bits
• Melody output
Melody frequency
Tone length
Tempo
Melody data
Buzzer driver signal output
• LCD driver
Number of segments
Duty
Bias
Frame frequency
Contrast
Display modes
: 529 Hz to 2979 Hz
: 63 varieties
: 15 varieties
: Stored in program memory
: 4 kHz
:
:
:
:
1024 Max. (64 SEG. × 16 COM.)
Selectable as 1/1 to 1/16 duty
Selectable as 1/4 or 1/5 bias (regulator built-in)
ex. 64 Hz (at 1/16 duty), 128 Hz (at 1/8 duty), 256 Hz (at 1/4 duty),
512 Hz (at 1/2 duty), 1024 Hz (at 1/1 duty)
: 16 levels adjustable
: Selectable as all-ON mode/all-OFF mode/power down mode/
normal display mode
: (8 bits)×(8 bits)
→
Product (16 bits)
: (16 bits)/(8 bits)
→
Quotient (16 bits), Remainder (8 bits)
• Multiplier/divider circuit
Multiplier
Divider
• System reset function
System reset through RESET pin (selectable as built-in 2 kHz RESET-Sampling circuit by mask option)
System reset by power-on detection (When not using 2 kHz RESET-Sampling circuit)
System reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
The value of the judgment voltage is selected by the software (by setting the LD1 and LD0 bits of BLDCON).
LD1
0
0
1
1
LD0
0
1
0
1
Judgment Voltage (V)
1.05
±
0.10
1.20
±
0.10
1.80
±
0.10
2.40
±
0.10
Remarks
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
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