FEDL63187B-06
Semiconductor
1
ML63187B/63189B
BLOCK DIAGRAM (ML63189B)
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied to the circuits
corresponding to the signal names inside
from V
DDI
(power supply for interface).
CPU CORE
CBR
H
nX-4/250
L
RA
PC
TIMING
CON-
TROL
ROM
32 KW
EBR
SP
RSP
X
Y
C
A
G
MIE
Z
BUS
CON-
TROL
ALU
STACK
CAL : 16-level
REG : 16-level
INSTRUCTION
DECODER
IR
INT
4
RAM
1536N
TIMER
8 bit
×
4
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
INT
RESET
RST
INT
4
TST1
TST2
TST
TBC
DATA BUS
INT
1
MELODY
INT189
1
SFT
SCLK*
SIN*
SOUT*
MD
MDB
BLD
XT0
XT1
OSC
OSC0
OSC1
INT
1
INT
1
WDT
100 HzTC
INT
1
INPUT
PORT
P0.0-P0.3
V
DDH
V
DD
CB1
CB2
V
DD1
V
DD2
V
DD3
V
DD4
V
DD5
C1
C2
V
DDL
BIAS
LCD
&
DSPR
INT
2
BACK
UP
I/O
PORT
P9.0-P9.3
PA.0-PA.3
PB.0-PB.3
PE.0-PE.3
COM1-16
SEG0-63
V
DDI
V
SS
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