FEDL63187B-06
1Semiconductor
ML63187B/63189B
BLOCK DIAGRAM (ML63189B)
An asterisk (*) indicates the port secondary function.
indicates that the power is supplied to the circuits
corresponding to the signal names inside
from VDDI (power supply for interface).
CPU CORE
nX-4/250
H
X
L
CBR
EBR
RA
PC
TIMING
CON-
TROL
ROM
32 KW
Y
A
C
G
Z
SP
BUS
ALU
CON-
TROL
RSP
MIE
IR
INSTRUCTION
DECODER
STACK
CAL : 16-level
REG : 16-level
INT
4
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
TIMER
8 bit × 4
RAM
1536N
T13CK*
INT
1
INT189
RESET
SCLK*
SIN*
RST
SFT
INT
4
SOUT*
TBC
BLD
TST1
TST2
TST
INT
1
MD
MELODY
MDB
XT0
XT1
INT
1
INT
1
OSC
100 HzTC
WDT
OSC0
OSC1
INPUT
PORT
P0.0-P0.3
INT
1
VDDH
VDD
P9.0-P9.3
PA.0-PA.3
PB.0-PB.3
PE.0-PE.3
BACK
UP
I/O
PORT
CB1
CB2
VDD1
VDD2
VDD3
VDD4
VDD5
C1
INT
2
BIAS
LCD
&
DSPR
COM1-16
SEG0-63
C2
VDDI
VSS
VDDL
6/36
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