FEDL63187B-06
1Semiconductor
ML63187B/63189B
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I/O ports
Input ports:
Selectable as input with pull-up resistor/input with pull-down resistor/high-impedance
input
Input-output ports: Selectable as input with pull-up resistor/input with pull-down resistor/high-impedance
input
Selectable as P-channel open drain output/N-channel open drain output/CMOS
output/high-impedance output
Can be interfaced with external peripherals that use a different power supply than this device uses. VDD is the
power supply pin for ports.
Number of ports:
ML63187B
Input-output port
ML63189B
: 2 ports × 4 bits
Input port
Input-output port
: 1 port × 4 bits
: 4 ports × 4 bits
•
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Melody output
Melody frequency
Tone length
: 529 to 2979 Hz
: 63 types
: 15 types
: Resides in the program memory
: 4 kHz
Tempo
Melody data
Buzzer driver signal output
LCD driver
Number of segments
Duty
: 1024 Max. (64 SEG × 16 COM)
: 1/1 to 1/16 duty
Bias
: Selectable as 1/4 or 1/5 bias
regulator circuit built-in
Frame frequency
: 64 Hz (at 1/16 duty) , 128 Hz (at 1/8 duty ) , 256 Hz (at 1/4 duty) ,
512Hz (at 1/2 duty) , 1024 Hz (at 1/1 duty )
: A maximum of 16 levels adjustable
: Selectable s all-ON mode/all-OFF mode/power down mode/normal
display mode adjustable contrast.
Contrast
Display modes
•
•
System reset function
• System reset by RESET pin (Built-in 2 kHz RESET sampling circuit can be selected by mask option)
• System reset by power-on detection (When not using 2 kHz RESET sampling circuit)
• System reset by detection that low-speed clock has stopped oscillation
Battery check
Low-voltage supply check
The value of the judgment voltage is selected by the software by setting the LD1 and LD0 bits of BLDCON.
LD1
0
LD0
0
Judgment Voltage (V)
1.05 ± 0.10
Remarks
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
0
1
1.20 ± 0.10
1
0
1.80 ± 0.10
1
1
2.40 ± 0.10
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Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
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