¡ Semiconductor
FIFO Status Register 1 (C3h, –)
D7
D6
RFU
D5
D4
D3
D2
D1
D0
ML60851A
Receive FIFO0 Full (R)
RFU = 0000b
Receive FIFO0 Empty (R)
FIFO1 Full (R)
FIFO1 Empty (R)
FIFO Status Register 2 (C4h, –)
D7
RFU
D6
D5
D4
D3
D2
D1
D0
Transmit FIFO0 Full (R)
Transmit FIFO0 Empty (R)
FIFO2 Full (R)
RFU = 0000b
FIFO2 Empty (R)
FIFO3 Full (R)
FIFO3 Empty (R)
Endpoint Packet-Ready Register (C8h, 48h)
D7
D6
D5
D4
D3
RFU
D2
D1
D0
EP0 Receive Packet Ready (R/Reset)
EP1 Receive Packet Ready (R/Reset)
EP2 Receive Packet Ready (R/Reset)
EP0 Transmit Packet Ready (R/Set)
EP1 Transmit Packet Ready (R/Set)
EP2 Transmit Packet Ready (R/Set)
EP3 Transmit Packet Ready (R/Set)
Receive Packet Ready: When a valid packet arrives at an endpoint, this bit is automatically set and
the endpoint is locked. When "1" is written in this register, Receiver Packet Ready is reset and the
endpoint is unlocked. (This bit also is set to "0".)
When DMA is enabled, EP1 Receive Packet Ready is automatically reset after all the data in EP1 is
read during DMA transfer.
Transmit Packet Ready: When "1" is written in this register, the Transmit Packet Ready is set and the
packet in the corresponding endpoint is transmitted. Transmit Packet Ready is automatically reset
when the ACK handshake is returned from the host.
When DMA is enabled, EP1 Transmit Packet Ready is automatically set after the data written in EP1
reaches the maximum packet size during DMA transfer.
The value of this register remains unchanged when "0" is written in this register.
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