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s
ML53612
s
3.0 SIGNAL DESCRIPTIONS
Signal Description
[1]
Name
D_[7:0]
A_ [7:0]
ALE (AS)
CS_N
RD_N (STRB_N)
WR_N (R/W_N)
RESET
I_N (M)
CT_D_DISABLE
L_NETREF_[1:0]
L_SI_[1:0]
MC_TXD
APLL_CLKREF
APLL_VDDO
APLL_VDDC
APLL_PC
APLL_VCO
APLL_VSSC
APLL_VSSO
APLL_TEST
TEST
TMS
TCK
TRST_N
TDI
INT
CT_D_[31:0]
CT_FRAME_A_N
CT_C8_A
CT_NETREF_1
CT_NETREF_2
CT_FRAME_B_N
CT_C8_B
CT_MC
Description
Microprocessor Data Bus. (I/O, TTL Schmitt, 8 mA, 5V tolerant)
Microprocessor Address Bus. (Input, TTL Schmitt, 5V tolerant)
Intel Bus Mode - Address Latch Enable. Motorola Bus Mode - Address Strobe. The Microprocessor Address Bus A[9:0] is latched
internally on the falling edge of this signal. (Input, TTL Schmitt, 5V tolerant)
Chip Select. This active low signal selects the ML53612 for a microprocessor read or write operation. (Input, TTL Schmitt, 5V
tolerant)
Intel Bus Mode - Microprocessor Bus Read. Motorola Bus Mode - Microprocessor Bus Strobe. (Input, TTL Schmitt, 5V tolerant)
Intel Bus Mode - Microprocessor Bus Write. Motorola Bus Mode - Microprocessor Bus Read/Write signal.
(Input, TTL Schmitt, 5V tolerant)
Reset. This active high input signal initializes the microprocessor interface, configuration, and routing registers. (Input, TTL
Schmitt, 5V tolerant)
Microprocessor Bus Mode. When this input is low, Intel Bus Mode is selected. When this input is high, Motorola Bus Mode is
selected. (Input, TTL Schmitt, 5V tolerant)
CT_D Global disable. (I/O, TTL Schmitt, 8 mA, 50 k Pull Up, 5V tolerant)
Local Network Reference [1:0] Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
Local bus Serial Input Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
Message Channel Transmit Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
Analog PLL Clock Reference Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
+3.3 Volt Analog PLL I/O Power Supply
+3.3 Volt Analog PLL Core Power Supply
Analog PLL Phase Comparator Analog Output
Analog PLL VCO Analog Input
Analog PLL Core Ground
Analog PLL I/O Ground
Analog PLL Test Enable Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
Test Select. This input enables the pin continuity test. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
Test Access Port Mode Select. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
Test Access Port Clock. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
Test Access Port Reset. (active low). (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
Test Access Port Data Input. (Input, TTL Schmitt, 50 k Pull Up, 5V tolerant)
Interrupt Output. (I/O, TTL Schmitt, 50 k Pull Up, 8 mA, 5V tolerant)
CT Bus Serial Data Streams. (I/O, PCI, 5V tolerant)
CT Bus "A" Frame Sync. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
CT Bus "A" 8 MHz Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
CT Bus Network Reference 1. (I/O, PCI, 5V tolerant)
CT Bus Network Reference 2. (I/O, PCI, 5V tolerant)
CT Bus "B" Frame Sync. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
CT Bus "B" 8 MHz Clock. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
CT Bus Message Channel. (I/O, TTL Schmitt, 24 mA, 5V tolerant)
Oki Semiconductor
5
OKI [ OKI ELECTRONIC COMPONETS ]
