FEDL2500BFULL-02
OKI Semiconductor
ML2500BTA
PIN DESCRIPTIONS
Pin
5
6
4
3
2
Symbol
Dl
DO
SCK
CS
RESET
Type
l
O
l
l
l
Description
Serial input pin for command data.
Serial output pin for status data.
Shift clock input pin for the Dl and the DO pins.
Chip select pin. “L” level input enables data input/output through the serial
interface.
RESET input pin, resetting the serial interface circuit only. “L” level input to
this pin initializes the serial interface. Must input “L” pulse after each
power-on.
Insert a 30 kΩ resistor (Precision within ±1%) between this pin and the
DGND pin. The same resistor should also be inserted if an external clock
is used. The resistor value determines the frequency of the clock for
control in this device.
External clock input pin. Allowable clock frequency range is 4.0 to 8.192
MHz. When external clock is unused and internal oscillation clock is used,
connect this pin to the DGND.
Output “H” level during recording/playback operation.
Analog reference voltage (Signal Ground Voltage) output pin. It is
recommendable to insert a capacitor of 3300 pF or less between this pin
and the AGND pin. Loads except for capacitors should not be connected
to this pin.
Inverting input pin for the internal OP amplifier. Non-inverting input pin is
internally connected to SG voltage.
Output pin from the internal OP amplifier.
Analog waveform output. Connect to an amplifier to drive a SP.
Pins for testing the LSl. Must be held “OPEN”.
LSl’s testing pin. Must be connected to DGND.
Digital power supply pin. Insert a 0.1
µF
or larger by-pass capacitor
between this pin and the DGND pin.
Digital Ground pin
Analog power supply pin. Insert a 0.1
µF
or larger by-pass capacitor
between this pin and the AGND pin.
Analog Ground pin
15
ROSC
l
8
7
26
EXTCLK
MON
SG
l
O
O
31
30
27
10, 11, 13,
18, 20, 22,
28, 29
24
1
16
32
17
LIN
LOUT
AOUT
TEST2
TEST1
DV
DD
DGND
AV
DD
AGND
l
O
O
O
l
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OKI [ OKI ELECTRONIC COMPONETS ]
