FEDL22300DIGEST-01
OKI Semiconductor
ML22300 Family
PIN DESCRIPTIONS
Pin No.
21
symbol
I/O
I
Description
Place this pin at a “L” level when powered on. After the supply voltage is
settled, place this pin at a “H” level.
RESET
Sequence reset pin. The speech output and sequence output are stopped
in time tCHT after signal change. This output signal is disabled during POP
noise elimination.
12
SEQRST
I
Event specifying input pins.
EVIN0 (SW0)
EVIN1 (SW1)
EVIN2 (SW2)
EVIN3 (A0)
EVIN4 (A1)
EVIN5 (A2)
*Note 1
Event execution or stop can be performed by changes in the input signals
to the activation pins set by the EVIN0 pin or ROM option
Set the unused pins to be pulled up or pulled down.
When the MSM9800 series control mode is selected, addresses A0 to A2
after 16 ms are captured by changing the input signals to the SW0 to SW2
pins and the speech output is started. The SW0 to SW2 pins are pulled
down.
13
14
15
16
17
18
I
6
2
TEST
I
I
Input pin for testing. Fix this pin at a “L” level (DGND level).
Pin for connecting a crystal or a ceramic vibrator.
A feed back resistor (about 1 MΩ) is included between OSC1 and OSC2
pins.
OSC1
When a vibrator is used, place it as close to the LSI as possible.
Pin for connecting a crystal or a ceramic vibrator.
When a vibrator is used, place it as close to the LSI as possible.
3
OSC2
O
O
7
8
9
10
11
SEQ0
SEQ1
SEQ2
SEQ3
SEQ4
Sequencer output pins.
The patterns set by ROM option are output.
SEQ5/LED0
SEQ6/LED1
SEQ7/LED2
(BUSY)
23
24
25
Sequencer output pins.
The patterns set by ROM option are output.
And these pins can be set for the LED drive pins.
O
*Note 1
Pin for selecting the MSM9800 series control mode or ML22300 series
control mode. When powered on, the MSM9800 series control mode is
selected by placing this pin at a “L” level. When selecting the ML22300
series control mode, place this pin at any level other than the “L” level.
This output signal is the status output signal during event execution.
Active “L” or “H” can be selected by ROM option.
22
SEQEN
I/O
30
4
AOUT
VPP
*Note 2
O
Playback signal output pin.
Power supply pin for rewriting Flash memory.
Fix this pin to GND except when rewriting Flash memory.
Analog power supply pin.
Connect a capacitor of 0.1 μF or more between this pin and AGND.
Digital power supply pin.
Connect a capacitor of 0.1 μF or more between this pin and DGND.
Output pin of the regulator for the internal logic power supply.
Connect a electrolytic capacitor of 10 uF or more and a ceramic capacitor
of 0.1 μF or more between the VDDL and DGND pins.
Digital ground pin.
—
26
1
AVDD
DVDD
—
—
5
VDDL
—
20
28
DGND
AGND
—
—
Analog ground pin.
Notes: 1. The symbols in ( ) indicate the pin names when the MSM9800 series control mode is selected..
2. Applies to ML22Q310.
6/28
OKI [ OKI ELECTRONIC COMPONETS ]
