FEDL2250DIGEST-09
OKI Semiconductor
ML2250 family
PIN DESCRIPTIONS-1
ML2251/52/53/54/56-XXXGA and ML2253/54/56-XXXHB Common Pins
QFP
Pin
WCSP
pin
ML2256
WCSP pin
Symbol
Type
Description
When using the built-in ROM for voice output, this pin
outputs “L” level while channel 2 side processes a
command and while plays back voice.
BUSY2/ER
Works as ERRpin when using the EXT command for voice
output. If an abnormality occurred in the transfer of data,
the pin will output “L” level and the voice output may
become noisy.
43
A1
A1
O
R
“H” level at power on.
Outputs “L” level while the channel 1 side processes a
command and plays back voice.
“H” level at power on.
3
4
B2
A2
A2
B3
BUSY1
O
O
The command input of channel 2 side is valid at “H” level
when using the built-in ROM for voice output.
Works as DLpin when using EXT command for the voice
output. This pin outputs the signal that captures voice
data to inside. The data is captured inside on the rising
edge of DL.
NCR2/DL
“H” level at power on.
The command input of channel 1 side is valid at “H” level
when using the built-in ROM for voice output.
Works as NDR pin when using EXT command for the
voice output. The voice data input is valid at “H” level.
“H” level at power on.
NCR1/ND
R
5
C3
A3
O
At “L” level input, the device enters the initial state; the
oscillation stops, and AOUT output and DAQ output are
GND level at this time.
9
B4
A5
A5
B5
RESET
I
I
Test pin for the device.
Input “L” level to this pin. This pin has a pull-down resistor
built in.
10
TEST
Wired to a crystal or ceramic oscillator.
A feedback resistor of around 1 M is built in between this
XT pin and XTpin (pin 15).
When using an external clock, input the clock from this
pin.
14
15
A6
B6
A7
B7
XT
I
Wired to a ceramic or crystal oscillator.
When using an external clock, keep this pin open.
XT
O
16
18
19
20
E6
D5
D6
C5
D7
C5
C6
B6
D3
D2
D1
D0
CPU interface data bus pins in the parallel input interface.
I/O Channel status output pins at RDpin = “L” level.
In the serial input interface, keep these pins at “L” level.
CPU interface data bus pin in the parallel input interface.
When RDpin is at “L” level, this pin D4 usually outputs “L”
level.
21
E5
D6
D4
I/O
In the serial input interface, keep this pin at “L” level.
CPU interface data bus pin in the parallel input interface.
When RDpin is at “L” level, this D5/DO pin usually outputs
“L” level.
23
F6
E7
D5/DO
I/O Works as channel status output pin in the serial interface.
When CS and RD pins are “L” level, the status of each
channel is output serially from this D5/DO pin in
synchronization with SCK clock.
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