FEDL2201-01
Semiconductor
1
ML2201–XXX
PIN DESCRIPTION
Pin No.
Pin Name
I/O
The playback trigger pin.
ST
The number of pulses input to the
PI
pin, while this pin is held “L”,
determines the Phrase Address for playback. At the
ST’s
rising edge, the
phrase address data is loaded into the LSI and playback starts. When no
pulse input to
PI
occurs while this pin is held “L”, the LSI recognizes it as the
“Stop Code” that results in stopping playback.
The address input pin.
2
PI
I
The number of pulses input to this pin, while the
ST
pin is held “L”,
determines the Phrase Address for playback.
When 32 pulses are input, the internal counter returns to its initial value, “0”.
3
GND
—
The ground pin.
The analog output pin.
Configured as N-MOS open drain, analog signal is output in the form of
change in output (attraction) current. While the
PDWN
pin being held “H”,
this pin is sustained at 1/2 level and thus the current keeps on flowing.
When shifting to standby state and shifting back to ready state from
standby, the pop-noise canceller is put to work.
5
V
DD
—
The power supply pin.
Insert a 0.1
µF
bypass capacitor between this pin and the GND pin.
The external clock input pin.
6
XT
I
The ceramic resonator connection pin for ceramic oscillation option under
development.
Keep this pin open.
7
XT
O
The LSI’s operations may become unstable if this pin includes any
capacitive component.
The ceramic resonator connection pin for ceramic oscillation option under
development.
8
PDWN
I
The power down pin.
The LSI stays standby state while the pin being held “L”.
Description
1
I
4
AOUT
O
3/20
OKI [ OKI ELECTRONIC COMPONETS ]
