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MK32VT1672A-8YC 参数 Datasheet PDF下载

MK32VT1672A-8YC图片预览
型号: MK32VT1672A-8YC
PDF下载: 下载PDF文件 查看货源
内容描述: 16777216字X 72位同步动态RAM模块( 2BANK ) [16,777,216 Word x 72 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK)]
分类和应用: 存储动态存储器
文件页数/大小: 11 页 / 104 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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MK32VT1672A-8YC (98.07.06)  
AC CHARACTERISTIC  
(Vcc = 3.3V ± 0.3V, Ta = 0 ~ 70°C)  
NOTE 1, 2  
.
Parameter  
Symbol  
tCC  
Module Spec.  
Unit  
Note  
Min.  
Max.  
CL=3  
8
-
ns  
ns  
Clock Cycle Time  
CL=2  
CL=3  
CL=2  
12  
-
tAC  
3, 4  
3, 4  
-
6
ns  
Access Time from Clock  
-
10  
ns  
tCH  
tCL  
Clock "H" Pulse Time  
Clock "L" Pulse Time  
Input Setup Time  
Input Hold Time  
3
-
ns  
3
-
ns  
tSI  
2
-
ns  
tHI  
1
-
ns  
tOLZ  
tOHZ  
tOH  
Output Low Impedance Time from Clock  
Output High Impedance Time from Clock  
Output Hold from Clock  
3
-
ns  
-
8
ns  
3
3
-
ns  
tRC  
/RAS Cycle Time  
80  
-
ns  
tRP  
/RAS Precharge Time  
30  
-
ns  
tRAS  
tRCD  
tWR  
tRRD  
tREF  
tPDE  
tT  
/RAS Active Time  
48  
100,000  
ns  
/RAS to /CAS Delay Time  
Write Recovery Time  
20  
-
-
ns  
8
ns  
/RAS to /RAS Bank Active Delay Time  
Refresh Time  
16  
-
ns  
-
64  
-
ms  
ns  
tSI+1CLK  
-
Power-down Exit Set-up Time  
Input Level Transition Time  
/CAS to /CAS Delay Time (Min)  
Clock Disable Time from CKE  
Data Output High Impedance Time from  
DQMB  
3
ns  
ICCD  
ICKE  
IDOZ  
1
1
Cycle  
Cycle  
2
Cycle  
IDOD  
IDWD  
IROH  
Data Input Mask Time from DQMB  
0
0
3
2
Cycle  
Cycle  
Cycle  
Cycle  
Data Input Time from Write Command  
Data Output High Inpedance  
CL=3  
CL=2  
Time from Precharge Command  
IMRD  
Active Command Input Time from MODE  
Register Set Command Input (Min)  
2
2
Cycle  
Cycle  
IOWD  
Write Command Input Time from Output  
NOTES:  
1) AC measurements assume tT=1ns.  
2) The reference level for timing of input signals is 1.4V.  
3) This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF  
(RLoad is 50ohm).  
4) An access time is measured at 1.4V.  
5) If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL.  
1.4v  
50  
OUTPUT  
OUTPUT LOAD  
50pF