––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■
MG113P/114P/115P/73P/74P/75P FAMILY LISTING
60µm Staggered PAD products
No. of
Raw
Gates
MG113P/73P
Family 3LM
Usable Gates
MG114P/74P
Family 4LM
Usable Gates
MG115P/75P
Family 5LM
Usable Gates
No. of
Pads
No. of
Rows
No. of
Columns
SOG Base Array
EA Base Array
MG7xPB02
MG7xPB04
MG7xPB06
MG7xPB08
MG7xPB10
MG7xPB12
MG7xPB14
MG7xPB16
MG7xPB18
MG7xPB20
MG7xPB22
MG7xPB24
MG7xPB26
MG7xPB28
MG7xPB30
MG7xPB32
MG7xPB34
MG7xPB36
MG7xPB38
MG7xPB40
MG7xPB42
68
84
144
280
23,520
69,120
22,344
65,664
22,344
65,664
108
148
188
228
268
308
348
388
428
468
508
548
588
628
668
708
748
788
828
868
480
204
680
138,720
131,784
131,784
264
880
232,320
218,381
220,704
324
1,080
1,280
1,480
1,680
1,880
2,080
2,280
2,480
2,680
2,880
3,080
3,280
3,480
3,680
3,880
4,080
4,280
349,920
311,429
332,424
384
491,520
412,877
466,944
MG11xP14
MG11xP18
MG11xP22
444
657,120
387,701
572,573
732,974
519,125
611,122
504
846,720
635,040
745,114
564
1,060,320
1,297,920
1,559,920
1,845,120
2,154,720
2,488,320
2,845,920
3,227,520
3,633,120
4,062,720
4,516,320
4,993,920
5,495,520
763,430
901,272
624
882,586
1,025,357
1,154,045
1,310,035
1,465,210
1,642,291
1,821,389
2,001,062
2,179,872
2,356,378
2,529,139
2,696,717
2,857,670
684
982,498
744
1,107,072
1,249,738
1,393,459
1,536,797
1,678,310
1,816,560
1,950,106
2,077,507
2,197,325
2,308,118
804
MG11xP28
864
1,094,861
924
984
1,044
1,104
1,164
1,224
1,284
ARRAY ARCHITECTURE
The primary components of a 0.25µm MG113P/114P/115P circuit include:
• I/O base cells
• 60µm pad pitch
• Configurable I/O pads for V , V , or I/O (optimized 3-V I/O)
DD
SS
• V and V pads dedicated to wafer probing
DD
SS
• Separate power bus for output buffers
• Separate power bus for internal core logic and input buffers
• Core base cells containing N-channel and P-channel pairs, arranged in column of gates
• Isolated gate structure for reduced input capacitance and increased routing flexibility
• Innovative 4-transistor core cell architecture, licensed from In-Chip Systems, Inc
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads
per corner. The arrays also have separate power rings for the internal core functions (V
and V
)
DDC
SSC
and output drive transistors (V
and V ).
DDO
SSO
Oki Semiconductor
3
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