s
MG113P/114P/115P/73P/74P/75P
s
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FEATURES
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0.25µm drawn 3-, 4-, and 5-layer metal CMOS
Optimized 2.5-V core
Optimized 3-V I/O
SOG and CSA architecture availability
77-ps typical gate propagation delay (for a 4x-
drive inverter gate with a fanout of 2 and 0 mm
of wire, operating at 2.5 V)
Over 5.4M raw gates and 868 I/O pads using
60µ staggered I/O
User-configurable I/O with V
SS
, V
DD
, TTL,
3-state, and 1- to 24-mA options
Slew-rate-controlled outputs for low-radiated
noise
H-clock tree cells which reduces the maximum
skew for clock signals
• Low 0.2µW/MHz/gate power dissipation
• User-configurable single- and dual-port
memories
• Specialized IP cores and macrocells including
32-bit ARM7TDMI CPU, phase-locked loop
(PLL), and peripheral component interconnect
(PCI) cells
• Floorplanning for front-end simulation, back-
end layout controls, and link to synthesis
• Joint Test Action Group (JTAG) boundary scan
and scan path Automatic Test Pattern
Generation (ATPG)
• Support for popular CAE systems including
Cadence, IKOS, Mentor Graphics, Model
Technology, Inc. (MTI), Synopsys, and
Viewlogic
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2
Oki Semiconductor
OKI [ OKI ELECTRONIC COMPONETS ]
