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MD56V62400-10TA 参数 Datasheet PDF下载

MD56V62400-10TA图片预览
型号: MD56V62400-10TA
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 16MX4, 9ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 28 页 / 307 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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¡ Semiconductor
MD56V62400/H
PIN DESCRIPTION
CLK
CS
CKE
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE and DQM.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Address
Row & column multiplexed.
Row address: RA0 – RA11
Column address: CA0 – CA9
A12, A13
(BA1, BA0)
RAS
CAS
WE
DQM
DQi
Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal.
Data inputs/outputs are multiplexed on the same pin.
Functionality depends on the combination. For details, see the function truth table.
Bank Access pins. These pins are dedicated to select one of 4 banks.
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