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M7705 参数 Datasheet PDF下载

M7705图片预览
型号: M7705
PDF下载: 下载PDF文件 查看货源
内容描述: 4路单轨CODEC [4ch Single Rail CODEC]
分类和应用:
文件页数/大小: 20 页 / 144 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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¡ Semiconductor  
MSM7705-01/02/03  
DIN1, DIN2, DIN3  
PCM signal inputs for channels 1, 2, and 3 when the parallel mode is selected.  
D/A conversion is performed by the serial PCM signals to these pins, the RSYNC signals  
synchronous with the serial PCM signals, and the BCLK signal. Then the analog signals are  
output from AOUT1, AOUT2, and AOUT3 pins, respectively.  
The data rate of the PCM signal is equal to the frequency of the BCLK signal.  
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal  
register when shifted by eight bits.  
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.  
When the serial mode is selected, this pin is not used and should be connected to GND (0 V).  
DIN4  
PCM signal input for channel 4 when the parallel mode is selected.  
D/AconversionisperformedbytheserialPCMsignaltothispin,theRSYNCsignalsynchronous  
with the serial PCM signal, and the BCLK signal. Then the analog signal is output from AOUT4  
pin.  
The data rate of the PCM signal is equal to the frequency of the BCLK signal.  
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal  
register when shifted by eight bits.  
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.  
When the serial mode is selected, this pin is used for the 4ch multiplexed PCM signal input.  
BCLK  
Shift clock signal input for DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, DOUT3, and DOUT4.  
The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit  
and receive circuits to the power saving state.  
RSYNC  
Receive synchronizing signal input.  
EightbitsofPCMdatarequiredareselectedfromaseriesofPCMsignaltotheDIN1,DIN2,DIN3,  
and DIN4 pins by the receive synchronizing signal.  
All timing signals in the receive section are synchronized by this synchronizing signal. This  
signal must be synchronized in phase with the BCLK (generated from the same clock source as  
BCLK). The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are  
mainly the frequency characteristics of the receive section.  
However,thisdeviceoperatesintherangeof6kHzto10kHzunlessthefrequencycharacteristics  
of the system used are strictly specified, but the electrical characteristics specified in the data  
sheet are not guaranteed.  
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