s
KGL4208/KGL4209/KGL4210
s
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BLOCK DIAGRAM
V
DD
V
DD
V
DD
D
CBFF
CK
50
Ω
CR
C
Q
D
CBFF
Q
Q
Q
C
Q
Note: The number of KGL4208, 4209, and 4210 flip-flop stages are 2, 3, and 4, respectively.
CK
CR
Q
V
DD
Clock Input Terminal
Reference Voltage Bias Terminal
Divided Frequency Output Terminal
Power Supply of Internal Circuit
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Supply Voltage
Clock Input Voltage
Temperature at Package Base Under Bias
Storage Temperature
Symbol
V
DD
V
CI
Ts
Tst
Min.
-0.3
-0.3
-45
-45
Max.
2.3
1.5
100
125
Units
V
V
°C
°C
Exceeding these maximum ratings could cause immediate damage or lead to permanent deterioration of the device.
Electrical Characteristics
V
B
= 2 V ± 0.1 V, V
DD
= 2 V ± 0.1 V, Ts = 0°C to 70°C
Parameter
Operating Data Bit Rate Range
Power Dissipation
High-Level Clock Input Voltage
Low-Level Clock Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Symbol
DAR
PW
V
IH
V
IL
V
OH
V
OL
0.6
-0.1
0.5
0
Min.
Typ.
10
0.08
0.9
0.1
0.7
0.1
0.1
1.25
0.3
0.9
0.2
Max.
Units
Gbps
W
V
V
V
V
2
Oki Semiconductor