FEDS82V48540-01
OKI Semiconductor
MS82V48540
COMMAND OPERATION
Mode Register Set Command (CS,
RAS, CAS, WE
= “Low”)
The MS82V48540 has the mode register that defines the operation mode “CAS Latency, Burst Length, Burst
Sequence”. The Mode Register Set command should be executed just after the MS82V48540 is powered on.
Before entering this command, all banks must be precharged. Next command can be issued after t
RSC
.
Auto Refresh Command (CS,
RAS, CAS
= “Low”,
WE
= “High”)
The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be
performed 3,072 times within 64 ms and the next command can be issued after t
RC
from last Auto Refresh
command. Before entering this command, all banks must be precharged.
Self Refresh Entry/Exit Command (CS,
RAS, CAS, CKE
= “Low”,
WE
= “High”)
The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left “low”.
This operation terminates by making CKE level “high”. The self refresh operation is performed automatically by
the internal address counter on the MS82V48540 chip.
In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be
precharged. Next command can be issued after t
RC
.
Single Bank Precharge Command (CS,
RAS, WE,
A10/AP = “Low”,
CAS
= “High”)
The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA0 and
BA1.
All Banks Precharge Command (CS,
RAS, WE
= “Low”,
CAS,
A10/AP = “High”)
The All Bank Precharge command triggers precharge of all banks.
If this command is executed during special bank active mode, the special bank active mode is terminated.
Bank Active Command (CS,
RAS
= “Low”,
CAS, WE
= ”High”)
The Bank Active command activates the bank selected by BA0 and BA1. The Bank Active command corresponds
to conventional DRAM's
RAS
falling operation. Row addresses “A0 – A10, BA0 and BA1” are strobed.
Write Command (CS,
CAS, WE,
A10/AP = “Low”,
RAS
= “High”)
The Write command is required to begin burst write operation. Then burst access initial bit column address is
strobed.
Write with Auto Precharge Command (CS,
CAS, WE
= “Low”,
RAS,
A10/AP = “High”)
The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after
the burst write. Any command that interrupts this operation cannot be issued.
Read Command (CS,
CAS,
A10/AP = “Low”,
RAS, WE
= “High”)
The Read command is required to begin burst read operation. Then burst access initial bit column address is
strobed.
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