(PORT 2)
8
PORT2 BUS BUFFER
2 or 3
BLOCK DIAGRAM
PORT2 LATCH
(LOW4) AND
EXPANDER
PORT I/O
PORT2
LATCH
(HIGH4)
8
HIGHER PROGRAM
COUNTER (4)
4
PROGRAM MEMORY
(ROM)
1K¥8bits MSM80C48RS
2K¥8bits MSM80C49RS
4K¥8bits MSM80C50RS
INSTRUC-
TION
REGISTER
PLA
¡ Semiconductor
4
4
OSC FREQ
∏480
TEST1
TIMER/EVENT
COUNTER (8)
LOWER PROGRAM
COUNTER
(8)
BUS LATCH
AND LOW
PC TEMP
REGISTER
BUS
BUFFER
8
(DATA
BUS
PORT)
(8)
ACCUMULATOR
(8)
RAM ADDRESS
REGISTER
TEMP REG (8)
INT
FLAG0
FLAG1
TIMER FLAG
CARRY
ACC
ACC Bit TEST
FLAGS
TEST0
TEST1
MULTIPLEXER
ACCUMULATOR
LATCH
(8)
ARITHMETIC
LOGIC
UNIT
(8)
CONDI-
TIONAL
BRANCH
LOGIC
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
REGISTER 6
REGISTER 7
DECODER
8-LEVEL
STACK
OPTIONAL
SECOND
REGISTER
BANK
DATA STORE
DECIMAL
ADJUST
PORT1
BUS
BUFFER
AND
LATCH
8
(PORT 1)
CONTROL AND TIMING
ALE
READ
STROBE
WRITE
STROBE
INT
RESET
PROG
EA
XTAL1 XTAL2
PSEN
SS
RD
WR
DATA MEMORY (RAM)
64¥8 bits MSM80C48RS
128¥8 bits MSM80C49RS
256¥8 bits MSM80C50RS
MSM80C48/49/50, MSM80C35/39/40
INTERRUPT
OSCILLATOR
PROM/
PROGRAM
XTAL
EXPANDER
MEMORY
STROBE
ENABLE
ADDRESS LATCH,
SINGLE
INITIALIZE
CPU MEMORY
DATA LATCH
STEP
SEPARATE
STROBE CYCLE
CLOCK
2/20
OKI [ OKI ELECTRONIC COMPONETS ]
