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EI68C684 参数 Datasheet PDF下载

EI68C684图片预览
型号: EI68C684
PDF下载: 下载PDF文件 查看货源
内容描述: QUAD UART [QUAD UART]
分类和应用:
文件页数/大小: 2 页 / 38 K
品牌: IMP [ IMP, INC ]
 浏览型号EI68C684的Datasheet PDF文件第2页  
Part Numbers May Be Marked With "IMP" or "Ei."  
Ei82C684  
Ei68C684  
QUAD UART  
Semiconductor, Inc.  
Programmable internal clock:X1/CLK or  
X1/CLK divided by 2  
FEATURES  
Full duplex, four channel asynchronous  
receiver and transmitter  
Buffered system clock output pin  
Stand-by mode to reduce operating power  
Advanced CMOS low power technology  
Quadruple-buffered receiver and transmitter  
Internal bit rate generator with 23 industry  
standard bit rates operating from either of  
two standard crystal clocks  
DESCRIPTION  
Independent bit rate selection for each  
receiver and transmitter  
The Epic Ei68C684/Ei88C684 Quad Universal  
Asynchronous Receiver and Transmitter (QUART) is a  
data communication device that provides four fully  
independent full duplex asynchronous communication  
channels in a single package. The QUART is designed  
for use in microprocessor based systems and may be  
used in a polled or interrupt driven environment.  
Maximum bit rate: 1 x clock - 2 Mb/sec., 16  
x clock- 250 Kb/sec.  
Normal, auto-echo, local loop-back and  
remote loop-back modes  
Multi-function 16-bit counter/timer  
Programmable interrupt daisy chain  
Two basic versions of the QUART are pin selectable  
with SEL pin and each is optimized for use with various  
microprocessor families: the Ei88C684 for 8080/5,  
8086/88, Z80, Z8000, 68XX and 65XX family based  
systems., and the 68C681 for 68000 family based sys-  
tems.and the Ei68C684 for 68000family based systems  
A programmable mode of the Ei88C684 versions pro-  
vides an interrupt daisy chain for use in Z80 and Z8000  
based systems. The bus interfaces are however gener-  
al enough to allow interfacing with other microprocessors  
and microcontrollers. The Ei88C684 and Ei68C684 are  
high integrated versions of Epic Semiconductor’s  
Ei88C681 and Ei66C681 DUART’s respectively, and are  
function compatible with those devices.  
Up to 32 I/O pins (depending on package  
and version)  
Change of state detectors on inputs  
Multidrop mode compatible with 8051 nine-  
bit mode  
Stop bits programmable in 1/16-bit increments  
Pin selectable 88xxx/68xxx interface  
Debounced reset pin (20 nsec. min)  
On-chip oscillator for crystal  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
IP5  
IP4•  
RD•  
IP3  
IP2  
IP1(CTSB•)  
IP0(CTSA•)  
A1  
A2  
A3  
A4  
A5  
IP8(CTSC•)  
IP9(CTSD•)  
IP10  
IP11  
IEI  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
OP5  
OP6  
OP7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D0  
D1  
RXDA  
RDN  
D2  
IP1(CTSB)  
IP0(CTSA)  
A1  
D3  
D4  
Ei82C684  
Ei82C684  
D5  
A2  
D6  
A3  
D7  
D7  
A4  
WR•  
CE•  
OP15  
OP14  
OP13  
OP12  
R/WN  
CEN  
RXDD  
A5  
IP8(CTSC)  
IP9(CTSD)  
68-PIN PLCC  
44-PIN PLCC  
15  
For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com  
IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)