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EI16C450 参数 Datasheet PDF下载

EI16C450图片预览
型号: EI16C450
PDF下载: 下载PDF文件 查看货源
内容描述: 通用异步接收器 [Universal Asynchronous Receiver]
分类和应用:
文件页数/大小: 1 页 / 33 K
品牌: IMP [ IMP, INC ]
   
Ei16C450  
UART  
Semiconductor, Inc.  
Complete status reporting capabilities  
FEATURES  
Tri-State® TTL drive capabilities for bi-direc  
tional data bus and control bus  
5V Operation  
Full duplex asynchronous receiver and  
transmitter  
Line break generation and detection  
Internal diagnostic capabilities:  
Easily interfaces to most popular  
microprocessors  
- Loopback controls for communications link fault  
isolation  
Adds or deletes standard asynchronous com-  
munication bits (start, stop, and parity ) to or  
from a serial data stream  
- Break, parity overrun, and framing error simulation  
Fully prioritized interrupt systems controls  
Independently controlled transmitter, receiver,  
line status, and data set interrupts  
DESCRIPTION  
Programmable baud rate generator allows  
division of any input clock by 1 to (216-1) and  
generates the internal 16 x clock  
The Epic Ei16C450 Universal Asynchronous Receiver  
Transmitter (UART) is a CMOS-VLSI communication  
device in a single package.  
Independent receiver clock input  
The UART performs serial to parallel conversion  
on data characters received from a peripheral  
MODEM control functions (CTS, RTS, DSR,  
DTR, RI, and DCD)  
device or  
a
MODEM, and parallel-to-serial  
conversions on data characters received from the  
CPU. The CPU can read the complete status of the  
UART at any time during the functional operation.  
Status information reported includes the type and con-  
dition of the transfer operation being performed by the  
UART, as well as any error conditions (parity, overrun,  
framing, or break detect).  
Fully programmable serial interface characteris  
tics:  
- 5, 6, 7, or 8 bit characters  
- Even, odd, or no-parity bit generation and  
detection  
- 1, 1.5, or 2 stop bit generation  
- Baud generation (DC to 56k baud)  
Part Numbers May Be Marked With "IMP" or "Ei."  
False start bit detection  
PIN CONFIGURATION  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
RCLK  
SIN  
1
2
3
4
5
6
7
8
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
VCC  
RI•  
DCD•  
DSR•  
CTS•  
MR  
OUT1•  
DTR•  
RTS•  
OUT2•  
INTRPT  
NC  
A0  
A1  
A2  
ADS•  
CSOUT  
DDIS  
DISTR  
DISTR•  
N.C.  
D5  
1
2
3
4
5
6
7
8
9
36 N.C.  
35 RESET  
D6  
34 OP1  
39 MR  
D5  
D6  
D7  
RCLK 10  
SIN 11  
7
8
9
38 OUT1•  
37 DTR•  
36 RTS•  
35 OUT2•  
34 NC  
D7  
33 DTR  
E
i
RCLK  
N.C.  
RX  
32 RTS  
9
31 OP2  
1
6
C
4
5
0
Ei16C450  
Ei16C450  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
NC 12  
30 INT  
29 N.C.  
28 A0  
27 A1  
26 A2  
25 N.C.  
SOUT  
CS0  
CS1  
33 INTRPT  
32 NC  
SOUT 13  
CS0 14  
TX  
31 A0  
CS1 15  
CS0  
30 A1  
CS2• 16  
CS2•  
BAUDOUT•  
XTAL1  
XTAL2  
DOSTR•  
DOSTR  
VSS  
CS1 10  
29 A2  
BAUDOUT• 17  
CS2  
11  
12  
BAUDOUT  
40-PIN DIP  
44-PIN PLCC  
48-PIN TQFP  
5
For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com  
IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)