TECHNICAL DATA
IN74HCT573A
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
The IN74HCT573A is identical in pinout to the LS/ALS573. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High-Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the high-
impedance state. Thus, data may be latched even when the outputs are not
enabled.
ORDERING INFORMATION
IN74HCT573AN Plastic
IN74HCT573ADW SOIC
TA = -55° to 125° C for all packages
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TTL/NMOS-Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Latch
Enable Enable
Output
Q
PIN 20=VCC
PIN 10 = GND
Output
D
L
H
H
L
H
L
H
L
L
no change
Z
L
X
X
H
X
X = don’t care
Z = high impedance
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
