TECHNICAL DATA
IN74HC175A
Quad D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
The IN74HC175A is identical in pinout to the LS/ALS175. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate D inputs. Reset (active-low) is asynchronous
and occurs when a low level is applied to the Reset input. Information at a
D input is transferred to the corresponding Q output on the next positive-
going edge of the Clock input.
ORDERING INFORMATION
IN74HC175AN Plastic
IN74HC175AD SOIC
TA = -55° to 125° C for all packages
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock
X
Outputs
Reset
L
D
X
H
L
Q
L
H
L
Q
H
L
PIN 16=VCC
PIN 8 = GND
H
H
H
H
L
X
no change
X = Don’t care
Rev. 00