DATASHEET
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
ICS527-02
Description
Features
The ICS527-02 Clock Slicer is the most flexible way to
generate a CMOS output clock from a PECL input
clock with zero skew. The user can easily configure the
device to produce nearly any output clock that is
multiplied or divided from the input clock. The part
supports non-integer multiplications and divisions. A
SYNC pulse indicates when the rising clock edges are
aligned with zero skew. Using Phase-Locked Loop
(PLL) techniques, the device accepts an input clock up
to 200 MHz and produces an output clock up to 160
MHz.
• Packaged as 28-pin SSOP, Pb-free (150 mil body)
• Synchronizes fractional clocks rising edges
• PECL IN to CMOS OUT
• Pin selectable dividers
• Zero input to output skew
• User determines the output frequency—no software
needed
• Slices frequency or period
• Input clock frequency of 1.5 MHz to 200 MHz
• Output clock frequencies from 4 MHz to 160 MHz
• Very low jitter
• Duty cycle of 45/55
• Operating voltage of 3.3 V
The ICS527-02 aligns rising edges on PECLIN with
FBIN at a ratio determined by the reference and
feedback dividers.
For a PECL input and output clock with zero delay, use
the ICS527-04.
• Advanced, low-power CMOS process
• Industrial temperature version available
For a CMOS input and PECL output with zero delay,
use the ICS527-03.
Block Diagram
R6:R0
7
2
VDD
PECLIN
PECLIN
Reference
Divider
33 ohm
CLK1
Phase Comparator,
Charge Pump, and
Loop Filter
Output
Divider
VCO
Divide
by 2
33 ohm
1
0
FBIN
Feedback
Divider
CLK2
SYNC
Feedback can
come from
CLK1 or CLK2
(not both)
2
GND
DIV2
7
2
PDTS
F6:F0
S1:S0
IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 1
ICS527-02
REV J 051310
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
