DATASHEET
QUAD PLL FOR DTV
ICS487-25
Description
Features
The ICS487-25 generates five high-quality,
high-frequency clock outputs. It is designed to replace
crystals and crystal oscillators in DTV applications.
Using IDT’s patented Phase Locked Loop (PLL)
techniques, the device runs from a lower frequency
crystal or clock input.
• Packaged in 16-pin TSSOP
• Available in Pb-free packaging
• Replaces multiple crystals and oscillators
• Input crystal or clock frequency of 27 MHz
• Zero ppm frequency synthesis error
• Duty cycle of 45/55
Because there is zero ppm frequency synthesis error on
the audio clocks, the audio will remain locked to the
video.
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
VDD
3
2
S1:0
PLL1
PLL2
PLL3
ACLK
20M
48M
33.0M
X1/ICLK
X2
27 MHz
clock or
crystal
input
Crystal
Oscillator/
Clock
PLL4
3
24.576M
Buffer
External capacitors
may be required.
PDTS (all outputs and PLLs)
GND
IDT™ / ICS™ QUAD PLL FOR DTV
1
ICS487-25
REV B 092109
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
