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342M-XXLFT 参数 Datasheet PDF下载

342M-XXLFT图片预览
型号: 342M-XXLFT
PDF下载: 下载PDF文件 查看货源
内容描述: [Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8]
分类和应用: 时钟光电二极管外围集成电路晶体
文件页数/大小: 9 页 / 105 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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DATASHEET  
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER  
ICS342  
Description  
Features  
The ICS342 is a low cost, dual-output, field programmable  
clock synthesizer. The ICS342 can generate two output  
frequencies from 250 kHz to 200 MHz, using up to two  
independently configurable PLLs. The outputs may employ  
Spread Spectrum techniques to reduce system  
electro-magnetic interference (EMI).  
8-pin SOIC package (Pb-free)  
Highly accurate frequency generation  
M/N Multiplier PLL: M = 1...2048, N = 1...1024  
Output clock frequencies up to 200 MHz  
Two ROM locations for frequency and spread selection  
Spread spectrum capability for lower system EMI  
Center or Down Spread up to 4% total  
TM  
Using IDT’s VersaClock software to configure the PLL  
and output, the ICS342 contains a One-Time  
Programmable (OTP) ROM to allow field programmability.  
Programming features include 2 selectable configuration  
registers. Using Phase-Locked Loop (PLL) techniques, the  
device runs from a standard fundamental mode,  
inexpensive crystal, or clock. It can replace multiple crystals  
and oscillators, saving board space and cost.  
Selectable 32 kHz or 120 kHz modulation  
Input crystal frequency from 5 to 27 MHz  
Input clock frequency from 2 to 50 MHz  
Operating voltage of 3.3 V  
Advanced, low power CMOS process  
For one output clock, use the ICS341. For three output  
clocks, see the ICS343. For more than three outputs, see  
the ICS345 or ICS348.  
The device also has a power down feature that tri-states the  
clock outputs and turns off the PLLs when the PDTS pin is  
taken low.  
The ICS342 is also available in factory programmed custom  
versions for high-volume applications.  
Block Diagram  
VDD  
OTP ROM  
with PLL  
Divider  
SEL  
CLK1  
Values  
PLL Clock Synthesis,  
Spred Spectrum and  
Control Circuitry  
Crystal or  
clock input  
X1/ICLK  
Crystal  
Oscillator  
CLK2  
X2  
External capacitors are  
required with a crystal input.  
GND  
PDTS (both outputs and PLL)  
IDT® / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 1  
ICS342  
REV N 090613