FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
350MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843207-350
GENERAL DESCRIPTION
FEATURES
• Seven independently configurable LVPECL outputs at
87.5MHz, 175MHz or 350MHz
The ICS843207-350 is a low phase-noise
ICS
HiPerClockS™
frequency margining synthesizer that targets
clocking for high performance interfaces such
as SPI4.2 and is a member of the HiPerClockS™
family of high performance clock solutions from
• Individual high impedance control of each output
• Selectable crystal oscillator interface designed for 14MHz,
18pF parallel resonant crystal or LVCMOS single-ended input
IDT. In the default mode, each output can be configured
individually to generate an 87.5MHz, 175MHZ or 350MHz
LVPECL output clock signal from a 14MHz crystal input.
There is also a frequency margining mode available where
the device can be configured, using control pins, to vary
the output frequency up or down from nominal by 5%. The
ICS843207-350 is provided in a 48-pin LQFP package.
• Output frequency can be varied 5% from nominal
• VCO range: 620MHz - 750MHz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
1
VCCA
VCC
VCCO
nQ6
Q6
VCCO
Q0
36
35
34
33
2
BLOCK DIAGRAM
nQ0
Q1
3
ICS843207-350
4
Q0
00 HiZ
01 ÷2
10 ÷8
11 ÷4
nQ1
VEE
VCCO
Q2
5
32
31
30
48-Pin LQFP
7mm x 7mm x 1.4mm
package body
Y Package
VEE
6
nQ0
7
VCCO
nQ5
Q5
Pullup
Pullup
Pullup
Pullup
2
2
SEL[1:0]
8
29
28
27
Top View
nQ2
Q3
9
Q1
00 HiZ
01 ÷2
10 ÷8
11 ÷4
10
11
12
nQ4
Q4
nQ3
VCCO
26
25
nQ1
VCCO
13 14 15 16 17 18 19 20 21 22 23 24
SEL[3:2]
Q2
00 HiZ
01 ÷2
10 ÷8
11 ÷4
nQ2
2
2
2
SEL[5:4]
Pulldown
nPLL_SEL
XTAL_IN
14MHz
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q3
1
0
OSC
0
1
nQ3
0
1
XTAL_OUT
REF_CLK
SEL[7:6]
Phase
Detector
Predivider
÷2
VCO
620 - 750MHz
Pulldown
Q4
00 HiZ
01 ÷2
10 ÷8
11 ÷4
nQ4
Pulldown
nXTAL_SEL
Pullup
Pullup
Pullup
SEL[9:8]
0
1
÷50
÷95
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q5
nQ5
÷105
2
2
Pulldown
Pulldown
MODE
SEL[11:10]
MARGIN
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q6
To O/P Dividers
Pulldown
MR
nQ6
SEL[13:12]
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
1
ICS843207CY-350 REV. A DECEMBER 3, 2007
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
