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309RILFT 参数 Datasheet PDF下载

309RILFT图片预览
型号: 309RILFT
PDF下载: 下载PDF文件 查看货源
内容描述: [SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH]
分类和应用: 时钟PC光电二极管外围集成电路晶体
文件页数/大小: 10 页 / 123 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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DATASHEET  
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH  
ICS309  
Description  
Features  
The ICS309 is a versatile serially-programmable, triple  
PLL with spread spectrum clock source. The ICS309  
can generate any frequency from 250kHz to 200 MHz,  
and up to 6 different output frequencies simultaneously.  
The outputs can be reprogrammed on-the-fly, and will  
lock to a new frequency in 10 ms or less.  
Packaged in 20-pin SSOP (QSOP) – Pb-free, RoHS  
compliant  
Highly accurate frequency generation  
M/N Multiplier PLL: M = 1..2048, N = 1..1024  
Serially programmable: user determines the output  
frequency via a 3-wire interface  
To reduce system EMI emissions, spread spectrum is  
available that supports modulation frequencies of  
31 kHz and 120 kHz, as well as modulation amplitudes  
of +/-0.25% to +/-2.0%. Both center and down-spread  
options are available.  
Spread Spectrum frequency modulation for reduced  
system EMI  
Center or Down Spread up to 4% total  
Selectable 32 kHz and 120 kHz modulation  
Eliminates need for custom quartz oscillators  
Input crystal frequency of 5 - 27 MHz  
Input clock frequency of 3 - 50 MHz  
Output clock frequencies up to 200 MHz  
Operating voltage of 3.3 V  
The device includes a PDTS pin which tri-states the  
output clocks and powers down the entire chip.  
The ICS309 default for non-programmed start-up are  
buffered reference clock outputs on all clock output  
pins.  
TM  
IDT’s VersaClock programming software allows the  
user to configure up to 9 outputs with target  
Up to 9 reference clock outputs  
Power down tri-state mode  
frequencies, spread spectrum capabilities or buffered  
TM  
reference clock outputs. The VersaClock software  
automatically configures the PLLs for optimal overall  
performance.  
Very low jitter  
Block Diagram  
3
VDD  
PLL1 with  
Spread  
CLK1  
CLK2  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
CLK9  
STROBE  
Spectrum  
SCLK  
DATA  
Divide  
Logic  
and  
Output  
Enable  
Control  
PLL2  
PLL3  
Crystal or  
clock input  
X1/ICLK  
Crystal  
Oscillator  
X2  
GND  
2
External capacitors are  
required with a crystal input.  
PDTS  
IDT® SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH  
1
ICS309  
REV L 091311