欢迎访问ic37.com |
会员登录 免费注册
发布采购

280G-XXT 参数 Datasheet PDF下载

280G-XXT图片预览
型号: 280G-XXT
PDF下载: 下载PDF文件 查看货源
内容描述: [Clock Generator, 200MHz, CMOS, PDSO16, 0.173 INCH, TSSOP-16]
分类和应用: 时钟光电二极管外围集成电路晶体
文件页数/大小: 10 页 / 221 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
 浏览型号280G-XXT的Datasheet PDF文件第2页浏览型号280G-XXT的Datasheet PDF文件第3页浏览型号280G-XXT的Datasheet PDF文件第4页浏览型号280G-XXT的Datasheet PDF文件第5页浏览型号280G-XXT的Datasheet PDF文件第6页浏览型号280G-XXT的Datasheet PDF文件第7页浏览型号280G-XXT的Datasheet PDF文件第8页浏览型号280G-XXT的Datasheet PDF文件第9页  
DATASHEET  
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER ICS280  
Description  
Features  
The ICS280 field programmable spread spectrum clock  
synthesizer generates up to four high-quality,  
high-frequency clock outputs including multiple reference  
clocks from a low-frequency crystal input. It is designed to  
replace crystals, crystal oscillators and stand alone spread  
spectrum devices in most electronic systems.  
Packaged as 16-pin TSSOP  
Eight addressable registers  
Replaces multiple crystals and oscillators  
Output frequencies up to 200 MHz at 3.3 V  
Configurable Spread Spectrum Modulation  
Input crystal frequency of 5 to 27 MHz  
Input clock frequency of 3 to 166 MHz  
Up to four reference outputs  
TM  
Using IDT’s VersaClock software to configure PLLs and  
outputs, the ICS280 contains a One-Time Programmable  
(OTP) ROM for field programmability. Programming  
features include input/output frequencies, spread spectrum  
amount and eight selectable configuration registers.  
Operating voltages of 3.3 V  
Controllable output drive levels  
Advanced, low-power CMOS process  
Available in RoHS compliant packaging  
NOTE: EOL for non-green parts to occur on 5/13/10  
per PDN U-09-01  
Using Phase-Locked Loop (PLL) techniques, the device  
runs from a standard fundamental mode, inexpensive  
crystal, or clock. It can replace multiple crystals and  
oscillators, saving board space and cost.  
The ICS280 is also available in factory programmed custom  
versions for high-volume applications.  
Block Diagram  
3
VDD  
PLL1 with  
Spread  
Spectrum  
3
S2:S0  
OTP  
ROM  
CLK1  
CLK2  
CLK3  
CLK4  
with PLL  
Values  
Divide  
Logic  
and  
Output  
Enable  
Control  
PLL2  
PLL3  
Crystal or  
Clock Input  
X1/ICLK  
X2  
Crystal  
Oscillator  
3
GND  
External capacitors  
are required with a crystal input.  
PDTS  
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 1  
ICS280  
REV E 083109