DATASHEET
MULTIPLIER AND ZERO DELAY BUFFER
ICS2402
Description
Features
The ICS2402 is a high-performance Zero Delay Buffer
(ZDB) which integrates IDT’s proprietary analog/digital
Phase-Locked Loop (PLL) techniques. The chip is part
• 8-pin SOIC package
• Available in Pb (lead) free package
• Absolute jitter ±100 ps
• Propagation Delay of ±±00 ps
• Output multiplier of 2X
• Output clock frequency up to 80 MHz
TM
of IDT’s ClockBlocks family and was designed as a
performance upgrade to meet today’s higher speed and
lower voltage requirements. The zero delay feature
means that the rising edge of the input clock aligns with
the rising edges of both output clocks, giving the
appearance of no delay through the device.
• Can recover degraded input clock duty cycle
• Output clock duty cycle of 45/55
• Full CMOS clock swings with 25 mA drive capability
The ICS2402 is ideal for synchronizing outputs in a
large variety of systems, from personal computers to
data communications to graphics/video. By allowing
off-chip feedback paths, the device can eliminate the
delay through other devices.
at TTL levels
• Advanced, low power CMOS process
• Operating voltage of 3.3 V or 5 V
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
Phase
ICLK
Detector,
Charge
Pump,
S0
and
Loop
VCO
CLK1
Filter
divide
FBIN
by N
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER
1
ICS2402
REV E 081809
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
