IDT23S09E
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT23S09E
3.3V ZERO DELAY
CLOCK BUFFER, SPREAD
SPECTRUM COMPATIBLE
FEATURES:
DESCRIPTION:
• Phase-Lock Loop Clock Distribution
• 10MHz to 200MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer,
designedtoaddresshigh-speedclockdistributionapplications. Thezero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 200MHz.
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT23S09E-1 for Standard Drive
• IDT23S09E-1H for High Drive
TheIDT23S09Eisa16-pinversionoftheIDT23S05E. TheIDT23S09E
acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.
The-1Hversionofthisdeviceoperatesupto200MHzfrequencyandhas
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT23S09E enters power down. In this mode, the device will draw less
• No external RC network required
• Operates at 3.3V VDD
• Spread spectrum compatible
• Available in SOIC and TSSOP packages
than 12µA for Commercial Temperature range and less than 25µA for
Industrial temperature range, and the outputs are tri-stated.
The IDT23S09E is characterized for both Industrial and Commercial
operation.
FUNCTIONALBLOCKDIAGRAM
16
CLKOUT
2
CLKA1
PLL
1
REF
3
CLKA2
14
CLKA3
15
CLKA4
8
S2
Control
Logic
9
S1
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 2010
1
c
2006 Integrated Device Technology, Inc.
DSC - 6399/11
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
