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23S05T-1DCI 参数 Datasheet PDF下载

23S05T-1DCI图片预览
型号: 23S05T-1DCI
PDF下载: 下载PDF文件 查看货源
内容描述: [PLL Based Clock Driver, 23S Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8]
分类和应用: 驱动光电二极管逻辑集成电路
文件页数/大小: 7 页 / 89 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT23S05T  
2.5V ZERO DELAY CLOCK  
BUFFER, SPREAD SPECTRUM  
COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT23S05T is a high-speed phase-lock loop (PLL) clock buffer,  
designedtoaddresshigh-speedclockdistributionapplications. Thezero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT23S05T is an 8-pin version of the IDT23S09T. IDT23S05T  
acceptsonereferenceinput, anddrivesoutfivelowskewclocks. Allparts  
have on-chip PLLs which lock to an input clock on the REF pin. The PLL  
feedbackison-chipandisobtainedfromtheCLKOUTpad.Intheabsence  
of an input clock, the IDT23S05T enters power down. In this mode, the  
devicewilldraw lessthan12μA for Commercial Temperature Range and  
and less than 25μA for Industrial temperature range, the outputs are tri-  
stated, and the PLL is not running, resulting in a significant reduction of  
power. TheIDT23S05TischaracterizedforbothIndustrialandCommer-  
cialoperation.  
• Low jitter <200 ps cycle-to-cycle  
• No external RC network required  
• Operates at 2.5V VDD  
• Power down mode  
• Spread spectrum compatible  
• Available in SOIC package  
NOTE: EOL for non-green parts to occur on 5/13/10 per  
PDNU-09-01  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
APRIL 2012  
1
c
2012 Integrated Device Technology, Inc.  
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