IDT2309A
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT2309A
3.3V ZERO DELAY
CLOCK BUFFER
FEATURES:
DESCRIPTION:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer,
designedtoaddress high-speedclockdistributionapplications.Thezero
delayis achievedbyaligningthe phase betweenthe incomingclockand
the outputclock, operable withinthe range of10to133MHz.
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2309A-1 for Standard Drive
• IDT2309A-1H for High Drive
The IDT2309A is a 16-pin version of the IDT2305A. The IDT2309A
acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.
The-1Hversionofthis deviceoperates upto133MHzfrequencyandhas
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT2309Aenterspowerdown. Inthismode,thedevicewilldrawlessthan
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
12µAforCommercialTemperaturerangeandlessthan25µAforIndustrial
temperature range,andthe outputs are tri-stated.
The IDT2309A is characterized for both Industrial and Commercial
operation.
FUNCTIONALBLOCKDIAGRAM
16
CLKOUT
2
CLKA1
PLL
1
REF
3
CLKA2
14
CLKA3
15
CLKA4
8
S2
Control
Logic
9
S1
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
JULY 2004
1
c
2004 Integrated Device Technology, Inc.
DSC - 6588/5
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
