DATASHEET
3.3 VOLT ZERO DELAY LOW SKEW BUFFER
ICS2305
Description
Features
The ICS2305 is a low phase noise, high-speed PLL
based, low-skew zero delay buffer. Based on IDT’s
proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides four low skew outputs
at speeds up to 133 MHz at 3.3 V. The outputs can be
generated from the PLL (for zero delay), or directly from
the input (for testing), and can be set to tri-state mode
or to stop at a low level. The PLL feedback is on-chip
and is obtained from the CLKOUT pad.
• Clock outputs from 10 to 133 MHz
• Zero input-output delay
• Four low skew (<250 ps) outputs
• Device-to-device skew <700 ps
• Full CMOS outputs with 25 mA output drive
capability at TTL levels
• 5 V tolerant CLKIN
• Tri-state mode for board-level testing
• Advanced, low power, sub-micron CMOS process
• Operating voltage of 3.3 V
The ICS2305 is available in two different versions. The
ICS2305-1 is the base part. The ICS2305-1H is a high
drive version with faster rise and fall times.
• Industrial temperature range available
• Packaged in 8-pin SOIC
• Available in Pb (lead ) free package
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
VDD
PLL
CLKOUT
CLK1
CLKIN
CLK2
CLK3
CLK4
GND
IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
1
ICS2305
REV E 081709
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
