Integrated
Circuit
Systems, Inc.
ICS1524A
Dual Output Phase Controlled SSTL_3/PECL Clock Generator
General Description
Features
•
Wide input frequency range
The ICS1524A is a low-cost, very high-performance
frequency generator and phase controlled clock synthe-
sizer. It is perfectly suited to phase controlled clock
synthesis and distribution as well as line-locked and
genlocked applications.
• 8 kHz to 100 MHz
•
•
•
250 MHz balanced PECL differential outputs
150 MHz single-ended SSTL_3 clock outputs
Dynamic Phase Adjust (DPA) for DPACLK
outputs
The ICS1524A offers two channels of clock phase con-
trolled outputs; CLK and DPACLK. These two output
channels have both 250 MHz PECL differential and 150
MHz SSTL_3 single-ended output pins. The CLK output
channel has a fixed phase relationship to the PLL’s input
and the DPACLK uses the Dynamic Phase Adjust cir-
cuitry to allow control of the clock phase relative to input
signal.
• Software controlled phase adjustment
• 360o Adjustment down to 1/64 clock
increments
•
•
•
External or internal loop filter selection
Uses 3.3 VDC Inputs are 5 volt tolerant.
I2C-bus serial interface runs at either low speed
(100 kHz) or high speed (400 kHz).
Optionally, the CLK outputs can operate at half the clock
rate and phase aligned with the DPACLK channel, en-
abling deMUXing of multiplexed analog-to-digital
converters. The FUNC pin provides either the regener-
ated input from the phase-locked loop (PLL) divider
chain output or a re-synchronized and sharpened input
HSYNC.
•
Hardware and Software PLL Lock detection
Applications
•
•
•
Generic Frequency Synthesis
LCD Monitors and Projectors
Genlocking Multiple Video Systems
The advanced PLL uses either its internal program-
mable feedback divider or an external divider and is
programmed by a standard I2C-bus™ serial interface.
Block Diagram
Pin Configuration
Loop
Filter
IREF
CLK+
CLK–
DPACLK+ (PECL)
DPACLK– (PECL)
VSSQ
VDDQ
DPACLK (SSTL)
CLK
FUNC
VDDD
VSSD
SDA
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
(PECL)
(PECL)
CLK
SCL
CLK+/-
HSYNC
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
DPACLK
DPACLK+/-
FUNC
OSC
I2C
(SSTL)
(SSTL)
10
11
12
LOCK/REF (SSTL)
2
I CADR
OSC
24 Pin 300-mil SOIC
I2C-bus is a trademark of Philips Corporation.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
ICS1524A Rev D 12/23/2005
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
