IC41C82052S
IC41LV82052S
2M x 8 (16-MBIT) DYNAMIC
RAM
WITH ꢀAST PAGE MODE
ꢀEATURES
DESCRIPTION
ꢀAST Page Mode access cycle
TTL compatible inputs and outputs
Refresh Interval:
The ICSI 82052S Series is a 2,097,152 x 8-bit high-perfor-
mance CMOS Dynamic Random Access Memory. The &ast
Page Mode allows 2,048 random accesses within a single row
with access cycle time as short as 20 ns per 8-bit word.
Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden,
2,048 cycles/32 ms
These features make the 82052S Series ideally suited for high-
bandwidthgraphics, digitalsignalprocessing, high-performance
computing systems, and peripheral applications.
Self refresh Mode 2,048 cycles/128 ms
JEDEC standard pinout
Single power supply:
The 82052S Series is packaged in a 28-pin 300mil SOJ and a
28 pin TSOP-2
5V±10% or 3.3V ± 10%
Byte Write and Byte Read operation via
CAS
PRODUCT SERIES OVERVIEW
KEY TIMING PARAMETERS
Part No.
Refresh
2K
Voltage
5V ± 10%
3.3V ± 10%
Parameter
-50
50
13
25
20
84
-60 Unit
RAS Access Time (tRAC)
CAS Access Time (tCAC)
Column Address Access Time (tAA)
EDO Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
60
15
30
25
ns
ns
ns
ns
IC41C82052S
IC41LV82052S
2K
104 ns
PIN CONꢀIGURATION
28 Pin SOJ, TSOP-2
PIN DESCRIPTIONS
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
A0-A10 Address Inputs
2
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
I/O0-7
WE
Data Inputs/Outputs
Write Enable
3
4
5
OE
Output Enable
Row Address Strobe
Column Address Strobe
Power
6
RAS
CAS
Vcc
7
8
A10
A0
9
A8
10
11
12
13
14
A7
GND
NC
Ground
A1
A6
No Connection
A2
A5
A3
A4
VCC
GND
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR016-0A 06/12/2001
1
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
