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ICS1523 参数 Datasheet PDF下载

ICS1523图片预览
型号: ICS1523
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能可编程行同步时钟发生器 [High-Performance Programmable Line-Locked Clock Generator]
分类和应用: 时钟发生器
文件页数/大小: 27 页 / 1215 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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Integrated  
Circuit  
Systems, Inc.  
ICS1523  
High-PerformanceProgrammableLine-LockedClockGenerator  
General Description  
Features  
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Pixel clock frequencies up to 250 MHz  
The ICS1523 is a low-cost but very high-performance  
frequency generator for line-locked and genlocked high-  
resolution video applications. Using ICS’s advanced  
low-voltage CMOS mixed-mode technology, the ICS1523  
is an effective clock solution for video projectors and dis-  
plays at resolutions from VGA to beyond UXGA.  
Very low jitter  
Dynamic Phase Adjust (DPA) for clock outputs  
Balanced PECL differential outputs  
Single-ended SSTL_3 clock outputs  
Double-buffered PLL/DPAcontrol registers  
Independent software reset for PLL/DPA  
External or internal loop filter selection  
Uses 3.3Vdc. Inputs are 5V-tolerant.  
The ICS1523 offers pixel clock outputs in both differential  
(to 250 MHz) and single-ended (to 150 MHz) formats.  
Dynamic Phase Adjust™ circuitry allows user control of  
the pixel clock phase relative to the recovered sync signal.  
A second differential output at half the pixel clock rate  
enables deMUXing of multiplexed analog-to-digital con-  
verters. The FUNC pin provides either the regenerated  
input from the phase-locked loop (PLL) divider chain out-  
put or a re-synchronized and sharpened input HSYNC.  
I2C-bus™ serial interface can run at either low speed  
(100 kHz) or high speed (400 kHz).  
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Lock detection  
24-pin 300-mil SOIC package  
Applications  
The advanced PLL uses either its internal programmable  
feedback divider or an external divider. The device is pro-  
grammed by a standard I2C-bus™ serial interface and is  
available in a 24-pin wide small-outline integrated circuit  
(SOIC) package.  
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LCD monitors and video projectors  
Genlocking multiple video subsystems  
Frequency synthesis  
Block Diagram  
Pin Configuration  
24-Pin SOIC  
I2C-bus is a trademark of Philips Corporation.  
Dynamic Phase Adjust is a trademark of Integrated Circuit Systems, Inc.  
ICS reserves the right to make changes in the device data identified in  
this publication without further notice. ICS advises its customers to  
obtain the latest version of all device data to verify that any  
ICS1523 Rev S 5/21/99  
information being relied upon by the customer is current and accurate.