AV9173 -15
Integrated
Circuit
Systems, Inc.
Video Genlock PLL
General Description
Features
The AV9173-15 provides the analog circuit blocks required
for implementing a video genlock dot (pixel) clock
generator. It contains a phase detector, charge pump, loop
filter, and voltage-controlled oscillator (VCO). By grouping
these critical analog blocks into one IC and utilizing
external digital functions, performance and design
flexibility are optimized as are development time and
system cost.
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Phase-detector/VCO circuit block
Ideal for genlock system
Reference clock range 12 kHz to 1MHz
(see specification of output clock range)
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Output clock range 0.625 to 37.5 MHz for CLK1,
depending on input conditions (see Table 1) on page 2.
Provides h-sync capability with CLK1 outputs
15 to 37.5 MHz for 15kHz input
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On-chip loop filter
When used with an external clock divider, the AV9173-15
forms a Phase-Locked Loop configured as a frequency
synthesizer. The AV9173-15 is designed to accept video
horizontal synchronization (h-sync) pulses and produce a
video dot clock. A separated, negative-going sync input
reference pulse is required at pin 2 (IN).
Single 5 volt power supply
Low power CMOS technology
Small 8-pin DIP or SOIC package
The AV9173-15 is also suited for other clock recovery
applications in such areas as data communications.
Block Diagram
AV9173-15RevC051397P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
