ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS8305I is a low skew, 1-to-4, Differential/ • 4 LVCMOS/LVTTL outputs
ICS
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
• Selectable differential or LVCMOS/LVTTL clock inputs
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8305I has selectable clock inputs that accept
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
either differential or single ended input levels.The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin. Outputs are forced LOW when the clock is disabled. A sepa-
rate output enable pin controls whether the outputs are in the
active or high impedance state.
• LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 350MHz
• Output skew: 40ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
GND
OE
VDD
16
15
14
13
12
11
10
9
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
CLK_EN
D
Q
LE
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
LVCMOS_CLK
0
0
Q0
Q1
Q2
Q3
CLK
nCLK
1
1
GND
CLK_SEL
ICS8305I
16-LeadTSSOP
4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
OE
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
1
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
