Integrated Circuit Systems, Inc.
Document Type: Data Sheet
Document Stage: Preliminary
ICS1893AG
3.3 V 10Base-T/100Base-TX Integrated PHYceiver™
General
Features
The ICS1893AG is a re-packaged version of the ICS1893AF
in a 56-lead TSSOP 240 mil package. The ICS1893AG is a
fully integrated, Physical Layer device (PHY) that is
compliant with both the 10Base-T and 100Base-TX
CSMA/CD Ethernet Standard, ISO/IEC 8802-3. The
ICS1893AG uses the same proven silicon as the
ICS1893AF but offers a smaller form factor solution to users
where physical package size is important.
• Single 3.3 V ±10% power supply
• Supports category 5 cables with attenuation in excess of
24dB at 100 MHz across a temperature range from 0°C to
+70°C. Industrial temperature version is also available.
• DSP-based baseline wander correction to virtually
eliminate killer packets
• Low-power, 0.35-micron CMOS (typically 400 mW)
• Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sublayers of IEEE standard
• 10Base-T and 100Base-TX IEEE 802.3 compliant
All parametric specification and timing diagrams for the
ICS1893AF apply to the ICS1893AG. Refer to the
ICS1893AF datasheet for detailed specifications and timing.
• Clock or crystal supported
• Media Independent Interface (MII) supported
• Managed or Unmanaged Applications
• 10M or 100M Half and Full Duplex Modes
The ICS1893AG uses the same twisted-pair transmit and
receive circuits as the ICS1893AF, and the same
recommended board layout techniques apply to the
ICS1893AG.
• Auto-Negotiation with Next Page. Parallel detection for
Legacy products
• Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
The ICS1893AG is intended for Node applications using the
standard MII interface to the MAC.
• Loopback mode for Diagnostic Functions
• Small footprint 56-pin 240 mil TSSOP package.
ICS1893AG Block Diagram
100Base-TX
PCS
PMA
TP_PMD
•
•
Framer
CRS/COL
Detection
Parallel to Serial
4B/5B
•
•
•
•
Clock Recovery
Link Monitor
Signal Detection
Error Detection
•
•
•
•
MLT-3
10/100 MII
MAC
Interface
Twisted-
Pair
Interface to
Magnetics
Modulesand
RJ45
Interface
MUX
Integrated
Switch
Stream Cipher
Adaptive Equalizer
Baseline Wander
Correction
•
•
10Base-T
Connector
MII
Low-Jitter
Clock
Synthesizer
Auto-
Negotiation
Configuration
and Status
Extended
Register
Set
MII
Management
Interface
Clock
Power
LEDs and PHY
Address
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
ICS1893AG, Rev. A 04/14/05
April, 2005
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
