.
IBMN312164CT3 IBMN312804CT3
IBMN312404CT3
Preliminary
128Mb Synchronous DRAM - Die Revision B
Features
• Programmable CAS Latency: 2, 3
• High Performance:
-75H3 -75D3 -75A, -260, -360, -10,
CL=2 CL=3 CL=3 CL=2 CL=3 CL=3
• Programmable Burst Length: 1, 2, 4, 8
Units
• Programmable Wrap: Sequential or Interleave
Clock
Frequency
fCK
133 133 133 100 100 100 MHz
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard Power operation
tCK Clock Cycle
7.5
—
7.5
—
7.5
—
10
—
10
—
10
7
ns
ns
Clock Access
tAC
Time1
Clock Access
tAC
5.4
5.4
5.4
6
6
9
ns
Time2
1. Terminated load. See AC Characteristics on page 37.
2. Unterminated load. See AC Characteristics on page 37.
3. tRP = tRCD = 2 CKs
• 4096 refresh cycles/64ms
• Random Column Address every CK (1-N Rule)
• Single 3.3V ± 0.3V Power Supply
• LVTTL compatible
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BS0/BS1
(Bank Select)
• Package: 54-pin 400 mil TSOP-Type II
Description
The IBMN312404CT3, IBMN312804CT3, and
IBMN312164CT3 are four-bank Synchronous
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
and two bank select addresses (BS0, BS1) are
strobed with RAS. Eleven column addresses (A0-
A9, A11) plus bank select addresses and A10 are
strobed with CAS. Column address A11 is dropped
on the x8 device, and column addresses A11 and
A9 are dropped on the x16 device.
DRAMs organized as 8Mbit x 4 I/O x 4 Bank, 4Mbit x
8 I/O x 4 Bank, and 2Mbit x 16 I/O x 4 Bank, respec-
tively. These synchronous devices achieve high-
speed data transfer rates of up to 133MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM’s advanced 128Mbit single tran-
sistor CMOS DRAM process technology.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A11,
BS0, BS1 during a mode register set cycle. In addi-
tion, it is possible to program a multiple burst
sequence with single write cycle for write through
cache operation.
The device is designed to comply with all JEDEC
standards set for synchronous DRAM products,
both electrically and mechanically. All of the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 133MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Auto Refresh (CBR)
and Self Refresh operation are supported.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CK). Internal chip operating modes
are defined by combinations of these signals and a
command decoder initiates the necessary timings
for each operation. A fourteen bit address bus
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
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